The invention relates to a method for carrying out a burn-in process for electrically stressing a semiconductor memory.
Semiconductor memories are used to store information and can be realized as a semiconductor component. One semiconductor memory is e.g. a dynamic random access memory (DRAM). It contains a cell array with memory cells and an addressing periphery. The memory cells of the memory cell array contain a selection transistor and a storage capacitor. The addressing periphery is usually formed from transistors fabricated using CMOS technology. CMOS denotes Complimentary Metal Oxide Semiconductor and contains both N-MOS and P-MOS transistors.
In order to ensure that the transistors used have high reliability over the entire lifetime of a memory product, a burn-in process is carried out. The dictates of production result in that transistors are not able to maintain an identical behavior throughout their lifetime, which is reflected in an input and output characteristic curve that is changed over time. The change in the transistors is caused e.g. by xe2x80x9chot carrier injectionxe2x80x9d (injection of high-energy charge carriers), which affects transistors having a short channel length to an increasing extent. The threshold voltage of a freshly produced transistor is not stable since high-energy charge carriers are accumulating in the gate oxide when the transistor is operating. The introduction of a burn-in process makes it possible to stabilize the transistor properties at a constant value. The threshold stabilization is carried out during the burn-in phase, while the memory is in a test environment, so that the transistor has stable properties during operation. The burn-in processes are usually carried out in a furnace in which the memories are exposed to an elevated temperature. Documents that describe the performance of a burn-in include U.S. Pat. Nos. 5,976,899; 5,917,765; 5,898,186; 5,748,543; 5,636,171; and 6,018,485. Two documents that describe circuits for carrying out a burn-in process are U.S. Pat. Nos. 5,986,917 and 5,424,990. Further insights on the stressing of MOS transistors can be found in the reference by Zhi Chen et. al., titled xe2x80x9cOn the Mechanism for Interface Trap Generation in MOS Transistors Due to Channel Hot Carrier Stressingxe2x80x9d, IEEE Electron Device Letters, Vol. 21, No. 1, January 2000, p. 24.
It is accordingly an object of the invention to provide a method for carrying out a burn-in process for electrically stressing a semiconductor memory that overcomes the above-mentioned disadvantages of the prior art methods of this general type, which carries out a burn-in process for a memory and stabilizes the electrical characteristics of the memory.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for carrying out a burn-in process for electrically stressing semiconductor memories. The method includes providing a memory having a circuit configuration with a first voltage terminal, a second voltage terminal, a control input, and a MOS transistor. A reference-ground potential is applied to the first voltage terminal. A second voltage is applied to the second voltage terminal and a control voltage is applied to the control input, and the control voltage is then varied.
The mechanism on which the burn-in process according to the invention is based is dynamic stressing of a MOS transistor. In order to stress a MOS transistor, e.g. its source terminal is applied to a reference-ground potential, its drain terminal is applied to an operating voltage and its gate terminal is applied to an alternating voltage, which assumes values between the reference-ground potential and the operating voltage. The voltage at the drain terminal is chosen e.g. to be greater than the voltage at the gate terminal. Under these stress conditions, the properties of a transistor change as much in a few hours as in two years during normal operation. As a result, the threshold voltage of the stressed MOS transistor is stabilized and remains constant during normal operation in the memory during its expected 10-year operating life for the customer. Under the action of stress, for example the threshold voltage of the transistor is stabilized. Combinational blocks containing transistors are disposed in the circuit periphery. It is advantageous also that a defective transistor existing in the memory circuit periphery will be strongly degraded by stress and then easily identified as early as during the test phase, so that the defective memory is not supplied as a product.
In a development of the method according to the invention, the control voltage assumes voltage values which alternate between the reference-ground potential and an operating voltage. Accelerated aging of the circuit configuration is achieved by this procedure.
A further mode of the method according to the invention provides for the circuit configuration to contain a logic gate such as an inverter. The control voltage is applied to an inverter input, the reference-ground potential is applied to a first inverter voltage supply and the second voltage is applied to a second inverter voltage supply. The effect achieved by this configuration is that a transistor to be stressed is disposed in the circuit configuration. Furthermore, it is provided that the circuit configuration contains an inverter. An inverter, as the basic element of every CMOS circuit, is also contained in the circuit periphery of a memory. Moreover, logic gates and functions such as AND, NAND, OR, NOR, XOR etc., to be stressed and toggled by the control voltage, are contained in the circuit blocks.
In a development of the method according to the invention, the second voltage assumes the value of the operating voltage. By virtue of this configuration, the voltage difference between the reference-ground potential and the operating voltage is dropped across the circuit configuration.
An advantageous instance of the method according to the invention provides for the second voltage present at the second voltage terminal to alternate between the reference-ground potential and the operating voltage. The alternation of the second voltage increases the stress for the circuit configuration, so that the stressing time can be reduced and the same stress effect is achieved in a shorter time.
A development of the method according to the invention provides for the second voltage to alternate at a first frequency and the control voltage to alternate at a second frequency between the reference-ground potential and the operating voltage. The periodic alternation of the second voltage and control voltage at a fixed frequency in each case enables a simple circuitry realization of a configuration for carrying out a burn-in process.
An advantageous mode of the method according to the invention provides for the first frequency to be equal to the second frequency, and the two voltages to have a phase difference of between 150 and 210 degrees. A phase difference of 180 degrees results in that the two signals are exactly in antiphase. The tolerance range of between 150 and 210 degrees phase shift enables variation of the phase shift in the specified range, which results in a wide variety of stress configurations for the circuit configuration. A further advantageous configuration of the method according to the invention provides for the phase difference to be varied. A great variety of configurations of the operating voltage and the control voltage can be generated through the variation of the phase difference. As a result, the stress of the circuit configuration is increased further, which reduces the time for the burn-in process.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for carrying out a burn-in process for electrically stressing a semiconductor memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.